FRAM (Ferroelectric Random Access Memory) is a type of non-volatile memory device that uses such a ferroelectric capacitor and preserves stored information even when the power is off. Additionally, the FRAM has high-speed access, less power consumption, and excellent shock-resistance. Accordingly, the FRAM would be expected to be used as a main storage device for various electronic devices and equipment having file storing and retrieving functions, such as computers, networks and mobile devices.
In the FRAM, a memory cell is composed of the ferroelectric capacitor and a pass transistor, and which stores logical data “1” or “0” depending on polarization state of the ferroelectric capacitor. When a voltage is applied across the ferroelectric capacitor, a ferroelectric material is polarized according to the direction of an electric field. Hence, a threshold voltage at which a change in the polarization state of the ferroelectric material occurs is called a “coercive voltage”. In reading data stored in the memory cell, a voltage is applied between both electrodes of the ferroelectric capacitor to cause a potential difference, and accordingly excite charges on a bit line. The state of the data stored in the memory cell is sensed as a change in an amount of the charges excited on the bit line.
In FIG. 1, a circuit of the ferroelectric random access memory is illustrated, as a prior art, “A 0.25-um 3.0-V 1T1C 32-Mb Nonvolatile Ferroelectric RAM with Address Transition Detector and Current Forcing Sense Amplifier Scheme”, IEEE Journal of Solid-State Circuits, Vol. 37, No. 11, November 2002, wherein a word line 111 is connected to memory cells 150 and 151, next word line 112 is connected to memory cells 152 and 153, and last word line 113 is connected to memory cells 154 and 155. The memory cell 150 is composed of the pass transistor 156 and the ferroelectric capacitor 157. And plate lines 121 and 122 are connected to the capacitor of the memory cells. As shown in the figure, a plurality of memory cells is connected to single bit line for integrating more memory cells on a chip, so that the bit line is long and heavily loaded. With heavily loaded bit line, capacitance value of the ferroelectric capacitor should be big enough to drive the bit line for reading. And access time is slow because there is a waiting time before the bit line is redistributed by the charges of the ferroelectric capacitor.
In order to improve access time, hierarchical bit line architecture and multi-level cells are applied, as published, U.S. Pat. Nos. 6,240,007 and 7,304,881. However, differential amplifier is still used for sensing the stored data. As a result, the area is additionally increased, because the differential amplifier occupies relatively big space. Furthermore, the differential amplifier requires a reference voltage for comparing a voltage difference, which is one of difficult circuit with voltage and temperature variations, so that two memory cells store a data where one memory cell store positive data and another memory cell stores negative data for generating an inverted voltage reference.
And other prior art is published as U.S. Pat. No. 6,574,135 such that bit line is multi-divided into short lines for sharing a sense amplifier and a data buffer through the switch. However, bit line loading is still heavy, because the local bit line is connected to the global line through a transfer transistor when reading, which increases the effective capacitance of the local bit line. And one more prior art is published as U.S. Pat. No. 6,829,154 for dividing bit line into short lines. However, there is no adjustable gain sense amp for reading the memory cell more accurately. In this respect, there is still a need for improving the FRAM. More detailed explanation will be followed as below.